DBGE=0, BCE=0, FRF=0, SR=0, FEF=0, SEF=0, FWDE=0, FWF=0, FWIE=0, FR=0, FRIE=0, WSIE=0, RE=0, SEIE=0, WSF=0, FEIE=0, STOPE=0, FRDE=0
SAI Receive Control Register
| FRDE | FIFO request DMA enable 0 (0): Disables the DMA request. 1 (1): Enables the DMA request. |
| FWDE | FIFO warning DMA enable 0 (0): Disables the DMA request. 1 (1): Enables the DMA request. |
| FRIE | FIFO request interrupt enable 0 (0): Disables the interrupt. 1 (1): Enables the interrupt. |
| FWIE | FIFO warning interrupt enable 0 (0): Disables the interrupt. 1 (1): Enables the interrupt. |
| FEIE | FIFO error interrupt enable 0 (0): Disables the interrupt, 1 (1): Enables the interrupt. |
| SEIE | Sync error interrupt enable 0 (0): Disables interrupt. 1 (1): Enables interrupt. |
| WSIE | Word start interrupt enable 0 (0): Disables interrupt. 1 (1): Enables interrupt. |
| FRF | FIFO request flag 0 (0): Receive FIFO watermark not reached. 1 (1): Receive FIFO watermark has been reached. |
| FWF | FIFO warning flag 0 (0): No enabled receive FIFO is full. 1 (1): Enabled receive FIFO is full. |
| FEF | FIFO error flag 0 (0): Receive overflow not detected. 1 (1): Receive overflow detected. |
| SEF | Sync error flag 0 (0): Sync error not detected. 1 (1): Frame sync error detected. |
| WSF | Word start flag 0 (0): Start of word not detected. 1 (1): Start of word detected. |
| SR | Software reset 0 (0): No effect. 1 (1): Software reset. |
| FR | FIFO reset 0 (0): No effect. 1 (1): FIFO reset. |
| BCE | Bit Clock enable 0 (0): Receive bit clock is disabled 1 (1): Receive bit clock is enabled |
| DBGE | Debug enable 0 (0): Receiver is disabled in debug mode, after completing the current frame. 1 (1): Receiver is enabled in debug mode. |
| STOPE | Stop enable 0 (0): Receiver disabled in stop mode. 1 (1): Receiver enabled in stop mode. |
| RE | Receiver enable 0 (0): Receiver is disabled. 1 (1): Receiver is enabled, or receiver has been disabled and not end of frame. |